1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of controlling auto-refresh of the semiconductor device. More specifically, the present invention relates to a semiconductor memory device that refreshes a memory cell corresponding to an address generated by an internal address counter upon input of a predetermined command.
Priority is claimed on Japanese Patent Application No. 2009-011381, filed Jan. 21, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
A dynamic random access memory (DRAM) is a semiconductor memory device having a unit memory cell of a selection transistor and a data storage capacitor, selecting a specific memory cell out of plural memory cells by the use of a row/column address, and reading and writing data from and to the selected memory cell. However, the capacitor as a storage node is volatile and it is thus necessary to rewrite (refresh) data at a predetermined interval. In the specifications thereof, the number of refresh operations and the maximum refresh interval are determined. Japanese Unexamined Patent Application, First Publication, No. JP-A-2008-135113 discloses the followings. The refresh modes are classified into an auto-refresh (AREF) mode and a self refresh mode. The AREF is a mode in which a memory cell corresponding to an address generated by an internal address counter is performed in a tRFC period (a period from an AREF command to an ACT/AREF command) when the AREF command is input. After the refresh operation, the address counter is updated and is provided for the next AREF command.
The self refresh is a mode in which a refresh operation is performed every time at a frequency determined by an internal oscillation circuit (oscillator) while a CKE signal is in the “L” level, when the CKE (Clock Enable) signal is set to the “L” level at the same time as an REF command. In the self refresh mode, it is possible to adjust the trade-off relation between the current consumption and the data retention time by adjusting the period of the internal oscillator. Control methods of giving temperature dependency to the refresh period, changing the period using a temperature sensor, and the like have been performed as a method of reducing the current consumption in the self refresh mode. However, in the self refresh mode, since the CKE signal is in the “L” level, an external clock signal is not input to the DRAM. Accordingly, after it exits from the self refresh mode, there is a problem in that a long period of time is necessary for re-locking a synchronization circuit such as a DLL (Delay Lock Loop) and data cannot be read just after it exits from the self refresh mode.
On the other hand, in the AREF mode, data can be read just after the tRFC. Accordingly, the AREF mode has been often used when the system frequently operates. The AREF mode generally employs an 8K-refresh (8KREF) mode in the recent DRAM specification. The 8K-refresh mode is a mode in which an address is returned to an initial address after an AREF command is repeated 8192 times. However, when the data retention time is shortened for reasons of variation in the characteristics of a semiconductor device and the like, data may disappear even when it is intended to refresh the initial address after the 8192 times.